A CMOS based digital output buffer circuit and input buffer circuit, with both circuits forming a transceiver pair, is described. The transceiver enables high speed point-to-point digital communication and hence cannot be used for multi-drop digital buses. The transceiver offers many of the features desired of transceivers. These features include: a) Compliance between transmitting devices powered with one supply voltage to the receiving device powered with a differing supply voltage, b) Self-termination of the transmitted signal by the receiving circuitry. The self-termination absorbs the transmitted signal so that a portion of the received signal cannot be reflected back and forth between transmitter and receiver to interfere with subsequent transmitted signals. The self-termination also eliminates electrical stubs in packages which enclose CMOS digital integrated circuits, c) Low power operation, which is achieved by switching low currents to represent logic LOW and logic HIGH states. If even lower power is desired then the transceiver pair can be realized with the addition of a separate terminating supply voltage with a value much lower than the core operating voltage, d) Transceiver protocols such as bi-directional, power-down, and impedance control capabilities can be realized with our proposed transceiver circuits, e) Minimized susceptibility to simultaneous switching noise (SSN) effects, f) Compatibility with low impedance transmission lines, which allow for either greater intercconect density or lower crosstalk between adjacent signals, or a combination between these two benefits which accompany low impedance transmission lines.